1. Field of the Invention
This invention relates to a digital signal processor. More particularly, this invention relates to a digital signal processor which can input and output both fixed point data and floating point data.
2. Description of the Related Art
A digital signal processor (referred to hereinafter as DSP) is a microprocessor which carries out high speed calculations of floating point data, to thereby carry out a software processing of data which can not be processed by a general-purpose microcomputer when a real time processing of an audio signal, high speed video processing, and a motor control which requires a complicated and high speed processing, is needed.
As the calculation of data in the DSP is executed mainly in the floating point form which consists of a sign bit, an exponential part, and a mantissa part, the data input/output is performed in a floating point form where the DSP inputs data from or outputs data to another DSP. Further, the DSP is mainly used for processing analog signals, as mentioned above, and therefore, an analog to digital (A/D) converter is provided in a stage preceding a DSP or a series of DSP's, and a digital to analog (D/A) converter is provided in a stage following a DSP or a series of DSP's. Accordingly, since the A/D and D/A converters usually deal with digital data as integers, in particular, an integer of 16 bits in a Binary Two's Complement (BTC) code (wherein the maximum is 011 . . . 111, the minimum is 100 . . . 000, and 0 is 000 . . . 000) in an audio signal processing, preferably a DSP connected to the A/D converter can input the integer of the BTC code, and the DSP connected to the D/A converter can output the integer of the BTC code, as well as the floating point data. Most preferably, the DSP can convert the BTC to a floating point and/or the floating point to the BTC, by hardware logic. Note, the scale of the circuit which implements the above function must be kept as small as possible.
It is well known that the conversion from the BTC to the floating point and from the floating point to the BTC is most easily executed in the form of a Sign Magnitude Binary (SMB) code (wherein the maximum is 011 111, the minimum is 111 . . . 111, +0 is 000 . . . 000, and -0 is 100 . . . 000), as described, for example, in Unexamined Patent Publication (Kokai) No. 61-109139, because the SMB and the floating point are easily interconverted by a bits shift and counting operation.
The BTC code can be converted to the SMB code by replacing all of the bits except for the most significant bit (MSB) or a sign bit with the result of an exclusive OR of the bits, except for the MSB (i.e., F .rarw. S .sym. F: where F denotes the bits except for the MSB S denotes the MSB or a sign bit, and .sym. denotes an EOR operator). The SMB code can be converted to the BTC code by the same process as used for the conversion from the BTC to the SMB code, i.e., F .rarw.S .sym. F.
In the above process, however, a slight offset occurs when the value is negative. For example, 111 . . . 111 representing an integer -1 in the BTC code is converted to 100 . . . 000 which represents an integer -0 in the SMB code, and therefore, a means for executing an addition or subtraction of 1 is required to ensure an exact conversion. The exact conversion is performed in a circuit which implements F .rarw. F .sym. S+S, and this circuit requires an adder having the same number of bits as that of the data.
The exact conversion circuit as mentioned above, will, however, output an incorrect result when a BTC code 100 . . . 000, which is lower limit among the integers represented in the BTC code, is converted to the SMB code; i.e., the result will be 000 . . . 000, which is far from the desired value.